ID CVE-2023-34326
Summary The caching invalidation guidelines from the AMD-Vi specification (48882—Rev 3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction (see stale DMA mappings) if some fields of the DTE are updated but the IOMMU TLB is not flushed. Such stale DMA mappings can point to memory ranges not owned by the guest, thus allowing access to unindented memory regions.
References
Vulnerable Configurations
  • cpe:2.3:o:xen:xen:*:*:*:*:*:*:*:*
    cpe:2.3:o:xen:xen:*:*:*:*:*:*:*:*
CVSS
Base: None
Impact:
Exploitability:
CWE NVD-CWE-noinfo
CAPEC
Access
VectorComplexityAuthentication
Impact
ConfidentialityIntegrityAvailability
Last major update 11-01-2024 - 15:57
Published 05-01-2024 - 17:15
Last modified 11-01-2024 - 15:57
Back to Top