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    <title>Most recent entries from all</title>
    <link>https://vulnerability.circl.lu</link>
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    <lastBuildDate>Thu, 01 Oct 2026 20:35:00 +0000</lastBuildDate>
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      <title>CVE-2023-52481 — arm64: errata: Add Cortex-A520 speculative unprivileged load workaround</title>
      <link>https://vulnerability.circl.lu/vuln/cve-2023-52481</link>
      <description>&lt;p&gt;&lt;strong&gt;Affected:&lt;/strong&gt; Linux&lt;/p&gt;
&lt;p&gt;In the Linux kernel, the following vulnerability has been resolved:&lt;/p&gt;
&lt;p&gt;arm64: errata: Add Cortex-A520 speculative unprivileged load workaround&lt;/p&gt;
&lt;p&gt;Implement the workaround for ARM Cortex-A520 erratum 2966298. On an
affected Cortex-A520 core, a speculatively executed unprivileged load
might leak data from a privileged load via a cache side channel. The
issue only exists for loads within a translation regime with the same
translation (e.g. same ASID and VMID). Therefore, the issue only affects
the return to EL0.&lt;/p&gt;
&lt;p&gt;The workaround is to execute a TLBI before returning to EL0 after all
loads of privileged data. A non-shareable TLBI to any address is
sufficient.&lt;/p&gt;
&lt;p&gt;The workaround isn&amp;#39;t necessary if page table isolation (KPTI) is
enabled, but for simplicity it will be. Page table isolation should
normally be disabled for Cortex-A520 as it supports the CSV3 feature
and the E0PD feature (used when KASLR is enabled).&lt;/p&gt;</description>
      <content:encoded>&lt;p&gt;&lt;strong&gt;Affected:&lt;/strong&gt; Linux&lt;/p&gt;
&lt;p&gt;In the Linux kernel, the following vulnerability has been resolved:&lt;/p&gt;
&lt;p&gt;arm64: errata: Add Cortex-A520 speculative unprivileged load workaround&lt;/p&gt;
&lt;p&gt;Implement the workaround for ARM Cortex-A520 erratum 2966298. On an
affected Cortex-A520 core, a speculatively executed unprivileged load
might leak data from a privileged load via a cache side channel. The
issue only exists for loads within a translation regime with the same
translation (e.g. same ASID and VMID). Therefore, the issue only affects
the return to EL0.&lt;/p&gt;
&lt;p&gt;The workaround is to execute a TLBI before returning to EL0 after all
loads of privileged data. A non-shareable TLBI to any address is
sufficient.&lt;/p&gt;
&lt;p&gt;The workaround isn&amp;#39;t necessary if page table isolation (KPTI) is
enabled, but for simplicity it will be. Page table isolation should
normally be disabled for Cortex-A520 as it supports the CSV3 feature
and the E0PD feature (used when KASLR is enabled).&lt;/p&gt;</content:encoded>
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