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  <updated>2026-10-02T00:44:17.098466+00:00</updated>
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  <entry>
    <id>https://vulnerability.circl.lu/vuln/cve-2026-43191</id>
    <title>CVE-2026-43191 — drm/amd/display: Adjust PHY FSM transition to TX_EN-to-PLL_ON for TMDS on DCN35</title>
    <updated>2026-10-02T00:44:17.100359+00:00</updated>
    <content type="xhtml">
      <div xmlns="http://www.w3.org/1999/xhtml"><p><strong>Affected:</strong> Linux</p>
<p>In the Linux kernel, the following vulnerability has been resolved:</p>
<p>drm/amd/display: Adjust PHY FSM transition to TX_EN-to-PLL_ON for TMDS on DCN35</p>
<p>[Why]
A backport of the change made for DCN401 that addresses an issue where
we turn off the PHY PLL when disabling TMDS output, which causes the
OTG to remain stuck.</p>
<p>The OTG being stuck can lead to a hang in the DCHVM's ability to ACK
invalidations when it thinks the HUBP is still on but it's not receiving
global sync.</p>
<p>The transition to PLL_ON needs to be atomic as there's no guarantee
that the thread isn't pre-empted or is able to complete before the
IOMMU watchdog times out.</p>
<p>[How]
Backport the implementation from dcn401 back to dcn35.</p>
<p>There's a functional difference in when the eDP output is disabled in
dcn401 code so we don't want to utilize it directly.</p></div>
    </content>
    <link href="https://vulnerability.circl.lu/vuln/cve-2026-43191"/>
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