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  <updated>2026-10-04T06:35:29.985691+00:00</updated>
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  <entry>
    <id>https://vulnerability.circl.lu/vuln/cve-2025-38055</id>
    <title>CVE-2025-38055 — perf/x86/intel: Fix segfault with PEBS-via-PT with sample_freq</title>
    <updated>2026-10-04T06:35:29.988961+00:00</updated>
    <content type="xhtml">
      <div xmlns="http://www.w3.org/1999/xhtml"><p><strong>Affected:</strong> Linux</p>
<p>In the Linux kernel, the following vulnerability has been resolved:</p>
<p>perf/x86/intel: Fix segfault with PEBS-via-PT with sample_freq</p>
<p>Currently, using PEBS-via-PT with a sample frequency instead of a sample
period, causes a segfault.  For example:</p>
<p>BUG: kernel NULL pointer dereference, address: 0000000000000195
    &lt;NMI&gt;
    ? __die_body.cold+0x19/0x27
    ? page_fault_oops+0xca/0x290
    ? exc_page_fault+0x7e/0x1b0
    ? asm_exc_page_fault+0x26/0x30
    ? intel_pmu_pebs_event_update_no_drain+0x40/0x60
    ? intel_pmu_pebs_event_update_no_drain+0x32/0x60
    intel_pmu_drain_pebs_icl+0x333/0x350
    handle_pmi_common+0x272/0x3c0
    intel_pmu_handle_irq+0x10a/0x2e0
    perf_event_nmi_handler+0x2a/0x50</p>
<p>That happens because intel_pmu_pebs_event_update_no_drain() assumes all the
pebs_enabled bits represent counter indexes, which is not always the case.
In this particular case, bits 60 and 61 are set for PEBS-via-PT purposes.</p>
<p>The behaviour of PEBS-via-PT with sample frequency is questionable because
although a PMI is generated (PEBS_PMI_AFTER_EACH_RECORD), the period is not
adjusted anyway.</p>
<p>Putting that aside, fix intel_pmu_pebs_event_update_no_drain() by passing
the mask of counter bits instead of 'size'.  Note, prior to the Fixes
commit, 'size' would be limited to the maximum counter index, so the issue
was not hit.</p></div>
    </content>
    <link href="https://vulnerability.circl.lu/vuln/cve-2025-38055"/>
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