{"@ID": "1280", "@Name": "Access Control Check Implemented After Asset is Accessed", "@Abstraction": "Base", "@Structure": "Simple", "@Status": "Incomplete", "Description": "A product's hardware-based access control check occurs after the asset has been accessed.", "Extended_Description": {"xhtml:p": "The product implements a hardware-based access control check. The asset should be accessible only after the check is successful. If, however, this operation is not atomic and the asset is accessed before the check is complete, the security of the system may be compromised."}, "Related_Weaknesses": {"Related_Weakness": [{"@Nature": "ChildOf", "@CWE_ID": "696", "@View_ID": "1000", "@Ordinal": "Primary"}, {"@Nature": "ChildOf", "@CWE_ID": "284", "@View_ID": "1000"}]}, "Weakness_Ordinalities": {"Weakness_Ordinality": {"Ordinality": "Primary"}}, "Applicable_Platforms": {"Language": [{"@Name": "Verilog", "@Prevalence": "Undetermined"}, {"@Name": "VHDL", "@Prevalence": "Undetermined"}, {"@Class": "Not Language-Specific", "@Prevalence": "Undetermined"}], "Operating_System": {"@Class": "Not OS-Specific", "@Prevalence": "Undetermined"}, "Architecture": {"@Class": "Not Architecture-Specific", "@Prevalence": "Undetermined"}, "Technology": {"@Class": "Not Technology-Specific", "@Prevalence": "Undetermined"}}, "Modes_Of_Introduction": {"Introduction": {"Phase": "Implementation"}}, "Common_Consequences": {"Consequence": {"Scope": ["Access Control", "Confidentiality", "Integrity"], "Impact": ["Modify Memory", "Read Memory", "Modify Application Data", "Read Application Data", "Gain Privileges or Assume Identity", "Bypass Protection Mechanism"]}}, "Potential_Mitigations": {"Mitigation": {"Phase": "Implementation", "Description": "Implement the access control check first. Access should only be given to asset if agent is authorized."}}, "Demonstrative_Examples": {"Demonstrative_Example": {"@Demonstrative_Example_ID": "DX-187", "Intro_Text": "Assume that the module foo_bar implements a protected register. The register content is the asset. Only transactions made by user id (indicated by signal usr_id) 0x4 are allowed to modify the register contents. The signal grant_access is used to provide access.", "Example_Code": [{"@Nature": "Bad", "@Language": "Verilog", "xhtml:br": [null, null, null, null, null, null, null, null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": null, "xhtml:div": [{"@style": "margin-left:1em;", "#text": "data_out = 0;"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null], "#text": "data_out = (grant_access) ? data_in : data_out;\n\t\t\t\t  assign grant_access = (usr_id == 3'h4) ? 1'b1 : 1'b0;"}], "#text": "if (!rst_n)\n\t\t\t\t\n\t\t\t\telse"}, "#text": "module foo_bar(data_out, usr_id, data_in, clk, rst_n);\n       \t\t\t      output reg [7:0] data_out;\n       \t\t\t      input wire [2:0] usr_id;\n       \t\t\t      input wire [7:0] data_in; \n       \t\t\t      input wire clk, rst_n;\n       \t\t\t      wire grant_access;\n       \t\t\t      always @ (posedge clk or negedge rst_n)\n       \t\t\t      begin\n       \t\t\t      \n\t\t\t      end\n\t\t\t      endmodule"}, {"@Nature": "Good", "@Language": "Verilog", "xhtml:br": [null, null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null], "xhtml:div": [{"@style": "margin-left:1em;", "xhtml:br": null, "#text": "data_out = 0;"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null], "#text": "assign grant_access = (usr_id == 3'h4) ? 1'b1 : 1'b0;\n\t\t\t\t  data_out = (grant_access) ? data_in : data_out;"}], "#text": "if (!rst_n)\n\t\t\t\t\n\t\t\t\telse"}, "#text": "always @ (posedge clk or negedge rst_n)\n       \t\t\t      begin\n\t\t\t      \n\t\t\t      end\n       \t\t\t      endmodule"}], "Body_Text": ["This code uses Verilog blocking assignments for data_out and grant_access. Therefore, these assignments happen sequentially (i.e., data_out is updated to new value first, and grant_access is updated the next cycle) and not in parallel. Therefore, the asset data_out is allowed to be modified even before the access control check is complete and grant_access signal is set. Since grant_access does not have a reset value, it will be meta-stable and will randomly go to either 0 or 1.", "Flipping the order of the assignment of data_out and grant_access should solve the problem. The correct snippet of code is shown below."]}}, "Related_Attack_Patterns": {"Related_Attack_Pattern": {"@CAPEC_ID": "180"}}, "Mapping_Notes": {"Usage": "Allowed", "Rationale": "This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.", "Comments": "Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.", "Reasons": {"Reason": {"@Type": "Acceptable-Use"}}}, "Content_History": {"Submission": {"Submission_Name": "Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna, Narasimha Kumar V Mangipudi", "Submission_Organization": "Intel Corporation", "Submission_Date": "2020-02-12", "Submission_Version": "4.1", "Submission_ReleaseDate": "2020-02-24"}, "Modification": [{"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2020-08-20", "Modification_Version": "4.2", "Modification_ReleaseDate": "2020-08-20", "Modification_Comment": "updated Applicable_Platforms, Demonstrative_Examples, Description, Related_Attack_Patterns"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2022-10-13", "Modification_Version": "4.9", "Modification_ReleaseDate": "2022-10-13", "Modification_Comment": "updated Demonstrative_Examples"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2023-04-27", "Modification_Version": "4.11", "Modification_ReleaseDate": "2023-04-27", "Modification_Comment": "updated Relationships"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2023-06-29", "Modification_Version": "4.12", "Modification_ReleaseDate": "2023-06-29", "Modification_Comment": "updated Mapping_Notes"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2023-10-26", "Modification_Version": "4.13", "Modification_ReleaseDate": "2023-10-26", "Modification_Comment": "updated Demonstrative_Examples"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2025-12-11", "Modification_Version": "4.19", "Modification_ReleaseDate": "2025-12-11", "Modification_Comment": "updated Weakness_Ordinalities"}]}}