{"@ID": "1262", "@Name": "Improper Access Control for Register Interface", "@Abstraction": "Base", "@Structure": "Simple", "@Status": "Stable", "Description": "The product uses memory-mapped I/O registers that act as an interface to hardware functionality from software, but there is improper access control to those registers.", "Extended_Description": {"xhtml:p": "Software commonly accesses peripherals in a System-on-Chip (SoC) or other device through a memory-mapped register interface. Malicious software could tamper with any security-critical hardware data that is accessible directly or indirectly through the register interface, which could lead to a loss of confidentiality and integrity."}, "Related_Weaknesses": {"Related_Weakness": {"@Nature": "ChildOf", "@CWE_ID": "284", "@View_ID": "1000", "@Ordinal": "Primary"}}, "Weakness_Ordinalities": {"Weakness_Ordinality": {"Ordinality": "Primary"}}, "Applicable_Platforms": {"Language": {"@Class": "Not Language-Specific", "@Prevalence": "Undetermined"}, "Operating_System": {"@Class": "Not OS-Specific", "@Prevalence": "Undetermined"}, "Architecture": {"@Class": "Not Architecture-Specific", "@Prevalence": "Undetermined"}, "Technology": {"@Class": "Not Technology-Specific", "@Prevalence": "Undetermined"}}, "Modes_Of_Introduction": {"Introduction": [{"Phase": "Architecture and Design", "Note": "This weakness may be exploited if the register interface design does not adequately protect hardware assets from software."}, {"Phase": "Implementation", "Note": "Mis-implementation of access control policies may inadvertently allow access to hardware assets through the register interface."}]}, "Common_Consequences": {"Consequence": {"Scope": ["Confidentiality", "Integrity"], "Impact": ["Read Memory", "Read Application Data", "Modify Memory", "Modify Application Data", "Gain Privileges or Assume Identity", "Bypass Protection Mechanism", "Unexpected State", "Alter Execution Logic"], "Note": "Confidentiality of hardware assets may be violated if the protected information can be read out by software through the register interface. Registers storing security state, settings, other security-critical data may be corruptible by software without correctly implemented protections."}}, "Detection_Methods": {"Detection_Method": [{"Method": "Manual Analysis", "Description": "This is applicable in the Architecture phase before implementation started. Make sure access policy is specified for the entire memory map. Manual analysis may not ensure the implementation is correct.", "Effectiveness": "Moderate"}, {"Method": "Manual Analysis", "Description": "Registers controlling hardware should have access control implemented. This access control may be checked manually for correct implementation. Items to check consist of how are trusted parties set, how are trusted parties verified, how are accesses verified, etc. Effectiveness of a manual analysis will vary depending upon how complicated the interface is constructed.", "Effectiveness": "Moderate"}, {"Method": "Simulation / Emulation", "Description": "Functional simulation is applicable during the Implementation Phase. Testcases must be created and executed for memory mapped registers to verify adherence to the access control policy. This method can be effective, since functional verification needs to be performed on the design, and verification for this weakness will be included. There can be difficulty covering the entire memory space during the test.", "Effectiveness": "Moderate"}, {"Method": "Formal Verification", "Description": "Formal verification is applicable during the Implementation phase. Assertions need to be created in order to capture illegal register access scenarios and prove that they cannot occur. Formal methods are exhaustive and can be very effective, but creating the cases for large designs may be complex and difficult.", "Effectiveness": "High"}, {"Method": "Automated Analysis", "Description": "Information flow tracking can be applicable during the Implementation phase. Security sensitive data (assets) - for example, as stored in registers - is automatically tracked over time through the design to verify the data doesn't reach illegal destinations that violate the access policies for the memory map. This method can be very effective when used together with simulation and emulation, since detecting violations doesn't rely on specific scenarios or data values. This method does rely on simulation and emulation, so testcases must exist in order to use this method.", "Effectiveness": "High"}, {"Method": "Architecture or Design Review", "Description": "Manual documentation review of the system memory map, register specification, and permissions associated with accessing security-relevant functionality exposed via memory-mapped registers.", "Effectiveness": "Moderate"}, {"Method": "Fuzzing", "Description": "Perform penetration testing (either manual or semi-automated with fuzzing) to verify that access control mechanisms such as the memory protection units or on-chip bus firewall settings adequately protect critical hardware registers from software access.", "Effectiveness": "Moderate"}]}, "Potential_Mitigations": {"Mitigation": [{"Phase": "Architecture and Design", "Description": "Design proper policies for hardware register access from software."}, {"Phase": "Implementation", "Description": "Ensure that access control policies for register access are implemented in accordance with the specified design."}]}, "Demonstrative_Examples": {"Demonstrative_Example": [{"Intro_Text": "The register interface provides software access to hardware functionality. This functionality is an attack surface. This attack surface may be used to run untrusted code on the system through the register interface. As an example, cryptographic accelerators require a mechanism for software to select modes of operation and to provide plaintext or ciphertext data to be encrypted or decrypted as well as other functions. This functionality is commonly provided through registers.", "Example_Code": [{"@Nature": "Bad", "@Language": "Other", "#text": "Cryptographic key material stored in registers inside the cryptographic accelerator can be accessed by software."}, {"@Nature": "Good", "@Language": "Other", "#text": "Key material stored in registers should never be accessible to software. Even if software can provide a key, all read-back paths to software should be disabled."}]}, {"Intro_Text": "The example code is taken from the Control/Status Register (CSR) module inside the processor core of the HACK@DAC'19 buggy CVA6 SoC [REF-1340]. In RISC-V ISA [REF-1341], the CSR file contains different sets of registers with different privilege levels, e.g., user mode (U), supervisor mode (S), hypervisor mode (H), machine mode (M), and debug mode (D), with different read-write policies, read-only (RO) and read-write (RW). For example, machine mode, which is the highest privilege mode in a RISC-V system, registers should not be accessible in user, supervisor, or hypervisor modes.", "Example_Code": [{"@Nature": "Bad", "@Language": "Verilog", "xhtml:div": {"xhtml:div": {"@style": "margin-left:1em;", "xhtml:b": "if ((riscv::priv_lvl_t'(priv_lvl_o & csr_addr.csr_decode.priv_lvl) != csr_addr.csr_decode.priv_lvl) && !(csr_addr.address==riscv::CSR_MEPC)) begin", "xhtml:br": [null, null, null, null], "xhtml:div": [{"@style": "margin-left:1em;", "xhtml:br": [null, null], "#text": "csr_exception_o.cause = riscv::ILLEGAL_INSTR;\n\t\t\t\t\t\t\t\t\tcsr_exception_o.valid = 1'b1;"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null], "#text": "csr_exception_o.cause = riscv::ILLEGAL_INSTR;\n\t\t\t\t\t\t\t\t\tcsr_exception_o.valid = 1'b1;"}], "#text": "end\n\t\t\t\t\t\t\t\t// check access to debug mode only CSRs\n\t\t\t\t\t\t\t\tif (csr_addr_i[11:4] == 8'h7b && !debug_mode_q) begin\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\tend"}, "#text": "if (csr_we || csr_read) begin\n\t\t\t\t\t\t\t\n\t\t\t\t\t\t\tend"}}, {"@Nature": "Good", "@Language": "Verilog", "xhtml:div": {"xhtml:div": {"@style": "margin-left:1em;", "xhtml:b": "if ((riscv::priv_lvl_t'(priv_lvl_o & csr_addr.csr_decode.priv_lvl) != csr_addr.csr_decode.priv_lvl)) begin", "xhtml:br": [null, null, null, null], "xhtml:div": [{"@style": "margin-left:1em;", "xhtml:br": [null, null], "#text": "csr_exception_o.cause = riscv::ILLEGAL_INSTR;\n\t\t\t\t\t\t\t\t\tcsr_exception_o.valid = 1'b1;"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null], "#text": "csr_exception_o.cause = riscv::ILLEGAL_INSTR;\n\t\t\t\t\t\t\t\t\tcsr_exception_o.valid = 1'b1;"}], "#text": "end\n\t\t\t\t\t\t\t\t// check access to debug mode only CSRs\n\t\t\t\t\t\t\t\tif (csr_addr_i[11:4] == 8'h7b && !debug_mode_q) begin\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\tend"}, "#text": "if (csr_we || csr_read) begin\n\t\t\t\t\t\t\t\n\t\t\t\t\t\t\tend"}}], "Body_Text": ["The vulnerable example code allows the machine exception program counter (MEPC) register to be accessed from a user mode program by excluding the MEPC from the access control check. MEPC as per the RISC-V specification can be only written or read by machine mode code. Thus, the attacker in the user mode can run code in machine mode privilege (privilege escalation).", "To mitigate the issue, fix the privilege check so that it throws an Illegal Instruction Exception for user mode accesses to the MEPC register. [REF-1345]"]}]}, "Observed_Examples": {"Observed_Example": [{"Reference": "CVE-2014-2915", "Description": "virtualization product does not restrict access to debug and other processor registers in the hardware, allowing a crash of the host or guest OS", "Link": "https://www.cve.org/CVERecord?id=CVE-2014-2915"}, {"Reference": "CVE-2021-3011", "Description": "virtual interrupt controller in a virtualization product allows crash of host by writing a certain invalid value to a register, which triggers a fatal error instead of returning an error code", "Link": "https://www.cve.org/CVERecord?id=CVE-2021-3011"}, {"Reference": "CVE-2020-12446", "Description": "Driver exposes access to Model Specific Register (MSR) registers, allowing admin privileges.", "Link": "https://www.cve.org/CVERecord?id=CVE-2020-12446"}, {"Reference": "CVE-2015-2150", "Description": "Virtualization product does not restrict access to PCI command registers, allowing host crash from the guest.", "Link": "https://www.cve.org/CVERecord?id=CVE-2015-2150"}]}, "Related_Attack_Patterns": {"Related_Attack_Pattern": {"@CAPEC_ID": "680"}}, "References": {"Reference": [{"@External_Reference_ID": "REF-1340"}, {"@External_Reference_ID": "REF-1341"}, {"@External_Reference_ID": "REF-1345"}]}, "Mapping_Notes": {"Usage": "Allowed", "Rationale": "This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.", "Comments": "Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.", "Reasons": {"Reason": {"@Type": "Acceptable-Use"}}}, "Content_History": {"Submission": {"Submission_Name": "Nicole Fern", "Submission_Organization": "Cycuity (originally submitted as Tortuga Logic)", "Submission_Date": "2020-05-08", "Submission_Version": "4.1", "Submission_ReleaseDate": "2020-02-24"}, "Modification": [{"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2020-08-20", "Modification_Version": "4.2", "Modification_ReleaseDate": "2020-08-20", "Modification_Comment": "updated Common_Consequences, Demonstrative_Examples, Description, Maintenance_Notes, Modes_of_Introduction, Potential_Mitigations, Related_Attack_Patterns"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2021-10-28", "Modification_Version": "4.6", "Modification_ReleaseDate": "2021-10-28", "Modification_Comment": "updated Description, Detection_Factors, Name, Observed_Examples, Potential_Mitigations, Weakness_Ordinalities"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2022-04-28", "Modification_Version": "4.7", "Modification_ReleaseDate": "2022-04-28", "Modification_Comment": "updated Related_Attack_Patterns"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2023-04-27", "Modification_Version": "4.11", "Modification_ReleaseDate": "2023-04-27", "Modification_Comment": "updated Relationships"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2023-06-29", "Modification_Version": "4.12", "Modification_ReleaseDate": "2023-06-29", "Modification_Comment": "updated Demonstrative_Examples, Mapping_Notes, References"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2023-10-26", "Modification_Version": "4.13", "Modification_ReleaseDate": "2023-10-26", "Modification_Comment": "updated Demonstrative_Examples"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2025-09-09", "Modification_Version": "4.18", "Modification_ReleaseDate": "2025-09-09", "Modification_Comment": "updated Relationships"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2025-12-11", "Modification_Version": "4.19", "Modification_ReleaseDate": "2025-12-11", "Modification_Comment": "updated Demonstrative_Examples, References"}], "Contribution": [{"@Type": "Content", "Contribution_Name": "Anders Nordstrom, Alric Althoff", "Contribution_Organization": "Cycuity (originally submitted as Tortuga Logic)", "Contribution_Date": "2021-10-11", "Contribution_Comment": "Provided detection methods and observed examples"}, {"@Type": "Content", "Contribution_Name": "Nicole Fern", "Contribution_Organization": "Riscure", "Contribution_Date": "2021-10-12", "Contribution_Comment": "Provided detection methods"}, {"@Type": "Content", "Contribution_Name": "Shaza Zeitouni, Mohamadreza Rostami, Pouya Mahmoody, Ahmad-Reza Sadeghi", "Contribution_Organization": "Technical University of Darmstadt", "Contribution_Date": "2023-06-21", "Contribution_Comment": "suggested demonstrative example"}, {"@Type": "Content", "Contribution_Name": "Rahul Kande, Chen Chen, Jeyavijayan Rajendran", "Contribution_Organization": "Texas A&M University", "Contribution_Date": "2023-06-21", "Contribution_Comment": "suggested demonstrative example"}], "Previous_Entry_Name": {"@Date": "2021-10-28", "#text": "Register Interface Allows Software Access to Sensitive Data or Security Settings"}}}